verilog - Why am I getting a red wire for my out? - Electrical Engineering Stack Exchange
![Simple guide to Verilog Wire and Reg types [waynejohnson.net]](https://blog.waynejohnson.net/lib/exe/fetch.php/verilog:verilog-reg-wires.png "Simple guide to Verilog Wire and Reg types [waynejohnson.net]")
Simple guide to Verilog Wire and Reg types [waynejohnson.net]
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![Simple guide to Verilog Wire and Reg types [waynejohnson.net]](https://blog.waynejohnson.net/lib/exe/fetch.php/verilog:inner-output-to-wire.png "Simple guide to Verilog Wire and Reg types [waynejohnson.net]")
Simple guide to Verilog Wire and Reg types [waynejohnson.net]
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![Simple guide to Verilog Wire and Reg types [waynejohnson.net]](https://blog.waynejohnson.net/lib/exe/fetch.php/verilog:wire-reg-cover.png "Simple guide to Verilog Wire and Reg types [waynejohnson.net]")
Simple guide to Verilog Wire and Reg types [waynejohnson.net]
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